
$WORK_SPACE="E:/develop/frv232platform"
$FIEL_LIST_PATH="$WORK_SPACE\src\frvfilelist.f"
$TFIEL_LIST_PATH="$WORK_SPACE\src\src_gen\frvfilelist.f"
$FRV_CONFIG_PATH="$WORK_SPACE\src\frv_config.json"
$SIMULATE_SRC_FILEPATH="$WORK_SPACE/src/src_gen"
$SIMULATE_TB_FILEPATH="$WORK_SPACE/tb"
$MODELSIM_TCL="$WORK_SPACE\tb\modelsim\model_run.tcl"
$TOP_MODULE="tb_core"

python ./vpython/VPython.py $WORK_SPACE $FIEL_LIST_PATH $FRV_CONFIG_PATH $TFIEL_LIST_PATH
# this is a piece of shit
if ($args.Count -eq 0) {
    exit
}

if ($args[0] -eq "bs" ) {
    exit
}

if ($args[0] -eq "update" ) {
    git add -A
    git commit -m $args[1]
    git push 
    exit
}

if ($args[0] -eq "verify" ) {
    Write-Host "INFO: Start VERIFY"    
    cd $WORK_SPACE/tb/modelsim
    if ($args.Count -eq 2 -and $args[1] -eq "genwave") {
        vsim -c -do "do {$MODELSIM_TCL} $SIMULATE_SRC_FILEPATH $TOP_MODULE $SIMULATE_TB_FILEPATH genwave" -l simulate.log
    }else {
        vsim -c -do "do {$MODELSIM_TCL} $SIMULATE_SRC_FILEPATH $TOP_MODULE $SIMULATE_TB_FILEPATH" -l simulate.log
    }
    cd $WORK_SPACE
    exit
}

